1. Field of the Invention
The present invention relates to semiconductor package structures and methods of fabricating the same, and, more particularly, to a semiconductor package structure having reduced thickness and a method of fabricating the same.
2. Description of Related Art
While electronic products are becoming low-profiled and compact-sized, their package structures need to meet Joint Electronic Device Engineering Council (JEDEC) specifications. For example, although dynamic random access memory (DRAM) chips have been developed by a 40 nm (or less) process technology, the package structures of such chips need to be kept the same so as to have a ball pitch of 0.8 mm for PCB mounting. For such a package structure, a fan-out type wafer level packaging method can be used. In addition, DDR3 SDRAM (Double-Data-Rate Three Synchronous Dynamic Random Access Memory) is the latest computer memory specification, in which a window ball grid array (wBGA) packaging method can be used.
FIG. 1 is a cross-sectional view of a conventional wBGA semiconductor package structure. Referring to FIG. 1, the wBGA semiconductor package structure comprises a packaging substrate 10 and a semiconductor chip 11. The packaging substrate 10 has at least a cavity 100 formed therethrough. The semiconductor chip 11 has an active surface 11a and an opposite inactive surface 11b, and a plurality of electrode pads 111 are disposed on the active surface 11a. The semiconductor chip 11 is disposed on a surface of the packaging substrate 10 through the active surface 11a thereof so as to cover one end of the cavity 100. Then, through the use of wire bonding technology, a plurality of gold wires 12 are passed through the cavity 100 for electrically connecting the electrode pads 111 of the semiconductor chip 11 to conductive pads 13 formed on the other surface of the substrate 10. Further, a first encapsulant material 14 is formed to encapsulate the gold wires 12, and a second encapsulant material 15 is formed on the packaging substrate 10 to encapsulate the semiconductor chip 11. Finally, a plurality of solder balls 16 are disposed on the exposed conductive pads 13 of the packaging substrate 10. With this configuration, the overall height of the package structure (including the solder balls 16) is 1.1-1.2 mm.
However, in the above-described semiconductor package structure, the gold wires 12 passing through the cavity 100 for electrically connecting the electrode pads 111 of the semiconductor chip 11 and the conductive pads 13 on the other surface of the substrate 10 are quite long, thereby adversely affecting the signal transmission efficiency. Further, the gold wires 12 lead to higher material costs as the price of gold on the international market has risen significantly recently. Furthermore, since the gold wires 12 and the semiconductor chip 11 are encapsulated by the first encapsulant material 14 and the second encapsulant material 15, respectively, heat generated by the semiconductor chip 11 cannot be effectively dissipated. In addition, the package is not ideal for portable electronic products due to the relatively large thickness of the overall package structure.
Therefore, there is a need to provide a semiconductor package structure and a method of fabricating the same so as to overcome the above-described drawbacks.